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Please use this identifier to cite or link to this item: http://localhost:8080/xmlui/handle/123456789/3324
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dc.contributor.authorShah, Mihirkumar Vinodchandra-
dc.date.accessioned2023-07-06T21:41:08Z-
dc.date.available2023-07-06T21:41:08Z-
dc.date.issued2016-01-
dc.identifier.urihttp://localhost:8080/xmlui/handle/123456789/3324-
dc.publisherThe Maharaja Sayajirao University of Barodaen_US
dc.subjectHardware Softwareen_US
dc.subjectArchitectureen_US
dc.subjectAlgorithmsen_US
dc.subjectFabricen_US
dc.subjectElectrical Engineeringen_US
dc.titleHardware Software Co-design for Network Processor Architecture through Integration of Scheduling Algorithm for Switching Fabric using VLSIen_US
dc.typeThesisen_US
Appears in Collections:THESES-Elec. Engg.

Files in This Item:
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01_Title.pdf38.93 kBAdobe PDFView/Open
02_Acknowledgement.pdf59.24 kBAdobe PDFView/Open
03_Certificate.pdf51.85 kBAdobe PDFView/Open
04_Declaration.pdf27.7 kBAdobe PDFView/Open
05_Dedicated.pdf9.09 kBAdobe PDFView/Open
06_Abstract.pdf48.22 kBAdobe PDFView/Open
07_Content.pdf198.85 kBAdobe PDFView/Open
08_List of figures.pdf605.98 kBAdobe PDFView/Open
09_List of tables.pdf55.55 kBAdobe PDFView/Open
10_List of abbreviation.pdf64.9 kBAdobe PDFView/Open
11_Chapter 1.pdf728.18 kBAdobe PDFView/Open
12_Chapter 2.pdf1.23 MBAdobe PDFView/Open
13_Chapter 3.pdf3.9 MBAdobe PDFView/Open
14_Chapter 4.pdf1.43 MBAdobe PDFView/Open
15_Chapter 5.pdf2.32 MBAdobe PDFView/Open
16_Chapter 6.pdf2.25 MBAdobe PDFView/Open
17_Chapter 7.pdf433.26 kBAdobe PDFView/Open
18_Conclusion and future work.pdf138.82 kBAdobe PDFView/Open
19_Bibliography.pdf353.7 kBAdobe PDFView/Open
20_Appendix A.pdf58.76 kBAdobe PDFView/Open
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